X-Shooter CCD Detector System: Hardware Setup
Preamplifier
| Arm | VIS | UVB | ||
| Camera | shdetv | shdetb | ||
| CCD | MIT/LL CCID-20 | e2v CCD 44-82 | ||
| Preamplifier ID | VIS | UVB | ||
| I²C bus address | 3Da) | 3C | ||
| Channel/Amplifier | Channel 0/Left "a" amplifier | Channel 1/Right "b" amplifier | Channel 0/Left "l" amplifier | Channel 1/Right "r" amplifier |
| CCD output amplifier load | 3 k resistor | 3 k resistor | J511 (4.7mA) | J511 (4.7mA) |
| Gains: | ||||
| Low Gain setting | Gain 3 = 1.5 | Gain 3 = 1.5 | Gain 1 = 2.25 | Gain 1 = 2.25 |
| High Gain setting | Gain 3 = 2.25 | Gain 3 = 2.25 | Gain 1 = 2.25 | Gain 1 = 2.25 |
a) VIS preamplifier has been modified to respond to address "3D".
Video Board
| Arm | VIS | UVB | ||
| Camera | shdetv | shdetb | ||
| CCD | MIT/LL CCID-20 | e2v CCD 44-82 | ||
| Video board 0/Amplifier | Channel 0/Left "a" amplifier | Channel 1/Right "b" amplifier | Channel 2/Left "l" amplifier | Channel 3/Right "r" amplifier |
| Nominal gains: | ||||
| Low Gain (Gain 0) | 1.5 e-/ADU | 1.5 e-/ADU | 1.7 e-/ADU | 1.7 e-/ADU |
| High Gain (Gain 1) | 0.6 e-/ADU | 0.6 e-/ADU | 0.6 e-/ADU | 0.6 e-/ADU |
| Common gain resistor | R 44 = 620 R | R 48 = 620 R | R 52 = 620 R | R 56 = 620 R |
| Resistors for low gain | R 43 = 180 R | R 47 = 180 R | R 51= 120 R | R 55 = 120 R |
| Resistors for high gain | R 42 = 120 R | R 46 = 120 R | R 50 = 44 R | R 54 = 44 R |
| Video Offset Range | - 10 to 0 V | - 10 to 0 V | - 5 to 0 V | - 5 to 0 V |
| Clamp/Sample time constants: | ||||
| Filter 0 | C 21 = 100 pF (t = 150 ns) |
C 25 = 100 pF (t = 150 ns) |
C 29 = 100 pF (t = 150 ns) |
C 33 = 100 pF (t = 150 ns) |
| Filter 1 | C 22 = 220 pF (t = 500 ns) |
C 26 = 220 pF (t = 500 ns) |
C 30 = 220 pF (t = 500 ns) |
C 34 = 220 pF (t = 500 ns) |
| Filter 2 | C 23 = 1 nF (t = 1500 ns) |
C 27 = 1 nF (t = 1500 ns) |
C 31 = 1 nF (t = 1500 ns) |
C 35 = 1 nF (t = 1500 ns) |
| Filter 3 | C 24 = C 374 = 1 nF (t = 3000 ns) |
C 28 = C 375 = 1 nF (t = 3000 ns) |
C 32 = C 376 = 1 nF (t = 3000 ns) |
C 36 = C 377 = 1 nF (t = 3000 ns) |
Low gain of MIT/LL CCID-20 was set to 1.5 e-/ADU to fully utilize the dynamic range of the 16 bit ADC. Maximum well depth of 90 ke- is best sampled by the 65535 levels of the ADC at a gain 1.5 e-/ADU (90 ke-/65535).
Bias Board
Bias voltage setting, assignment and setting of hardwired protection limits of connector A on bias board 0, BRD_ANABIAS0, which provides the biases for the e2v CCD 44-82 of the UVB arm:
| PERIPH_ID | Bias No. | Bias Name | Low Limit [V] | High Limit [V] | Voltage [V] |
| ANA_PRESET_VOLT_A | 0 | OG1-R | - 8 | + 8 | - 3.5 |
| ANA_PRESET_VOLT_B | 1 | OG2-R | - 8 | + 8 | - 2.5 |
| ANA_PRESET_VOLT_C | 2 | OD-R | GND | + 30 | 23 |
| ANA_PRESET_VOLT_D | 3 | RD-R | GND | + 15 | 11.25 |
| ANA_PRESET_VOLT_E | 4 | JD-R | GND | + 30 | 25 |
| ANA_PRESET_VOLT_F | 5 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_G | 6 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_H | 7 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_I | 8 | OG1-L | - 8 | + 8 | - 3.5 |
| ANA_PRESET_VOLT_J | 9 | OG2-L | - 8 | + 8 | - 2.5 |
| ANA_PRESET_VOLT_K | 10 | OD-L | GND | + 30 | 23 |
| ANA_PRESET_VOLT_L | 11 | RD-L | GND | + 15 | 11.25 |
| ANA_PRESET_VOLT_M | 12 | JD-L | GND | + 30 | 25 |
| ANA_PRESET_VOLT_N | 13 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_O | 14 | DD-LR | GND | + 30 | 18 |
| ANA_PRESET_VOLT_P | 15 | (not used) | GND | + 8 | 0 |
"L" = e2v left amplifier "R" = e2v right amplifier
Bias voltage setting, assignment and setting of hardwired protection limits of connector B on bias board 0, BRD_ANABIAS0, which provides the biases for MIT/LL CCID-20 of the VIS arm:
| PERIPH_ID | Bias No. | Bias Name | Low Limit [V] | High Limit [V] | Voltage [V] |
| ANA_PRESET_VOLT_AA | 16 | OD-A | GND | + 30 | 19 |
| ANA_PRESET_VOLT_AB | 17 | OG-A | - 8 | + 8 | 0 |
| ANA_PRESET_VOLT_AC | 18 | RD-A | GND | + 15 | 12.5 |
| ANA_PRESET_VOLT_AD | 19 | SCP-A | GND | + 15 | 10 |
| ANA_PRESET_VOLT_AE | 20 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_AF | 21 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_AG | 22 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_AH | 23 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_AI | 24 | OD-B | GND | + 30 | 19 |
| ANA_PRESET_VOLT_AJ | 25 | OG-B | - 8 | + 8 | 0 |
| ANA_PRESET_VOLT_AK | 26 | RD-B | GND | + 15 | 12.5 |
| ANA_PRESET_VOLT_AL | 27 | SCP-B | GND | + 15 | 10 |
| ANA_PRESET_VOLT_AM | 28 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_AN | 29 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_AO | 30 | (not used) | GND | + 8 | 0 |
| ANA_PRESET_VOLT_AP | 31 | (not used) | GND | + 8 | 0 |
"A" = MIT/LL left amplifier "B" = MIT/LL right amplifier
Clock Board
The clock voltage settings and SIMM output resistors selected for best performance:
| Arm | UVB | VIS | |||||||
| CCD | e2v CCD 44-82 | MIT/LL CCID-20 | |||||||
| Board ID | BRD_CLKDRV0 | BRD_CLKDRV1 | |||||||
| Board BUS addressa) | 0 | 1 | |||||||
| SIMM/Clock No. | DAC ID CLKDRV_ | Nameb) c) | Output resistor | High Level [V] | Low Level [V] | Nameb) c) | Output resistor | High Level [V] | Low Level [V] |
| 0 | DAC0 | SWL | 50 R | - 5 | + 5 | SWA | 50 R | - 5 | + 5 |
| 1 | DAC1 | SWR | 50 R | - 5 | + 5 | SWB | 50 R | - 5 | + 5 |
| 2 | DAC2 | RF3 | 50 R | - 5 | + 5 | S3 | 50 R | - 3 | + 6 |
| 3 | DAC3 | RF2L | 50 R | - 5 | + 5 | S2A | 50 R | - 3 | + 6 |
| 4 | DAC4 | RF1L | 50 R | - 5 | + 5 | S1A | 50 R | - 3 | + 6 |
| 5 | DAC5 | RF2R | 50 R | - 5 | + 5 | S2B | 50 R | - 3 | + 6 |
| 6 | DAC6 | RF1R | 50 R | - 5 | + 5 | S1B | 50 R | - 3 | + 6 |
| 7 | DAC7 | DG | 50 R | - 6 | + 6 | (empty)d) | - | - | - |
| 8 | DAC8 | IF1 | 10 R | - 8 | + 2 | P1 | 10 R | - 6 | + 2 |
| 9 | DAC9 | IF2 | 10 R | - 8 | + 2 | P2 | 10 R | - 6 | + 2 |
| 10 | DAC10 | IF3 | 10 R | - 8 | + 2 | P3 | 10 R | - 6 | + 2 |
| 11 | DAC11 | (empty)d) | 10 R | 0 | 0 | (empty)d) | - | - | - |
| 12 | DAC12 | FRL | 10 R | - 6 | + 6 | RGA | 10 R | 0 | + 10 |
| 13 | DAC13 | FRR | 10 R | - 6 | + 6 | RGB | 10 R | 0 | + 10 |
a) Addresses are selected by changing jumpers on the clock board.
b) "L" = e2v left amplifier "R" = e2v right amplifier
"A" = MIT/LL left amplifier "B" = MIT/LL right amplifier
c) The clock phase names shown here are the ones used by the waveform generation program, WES.
d) To reduce power dissipation, only clocks used are populated with SIMMs.
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