DMA-Interface (CS-P-1877 - revision B)

Interface of Gigalink Bus to ULTRA-SPARC DMA controller

Features

• Double Euro size module
• Interface to DMA controller SCD 60
• Data rate 60 MByte/s

General Description

DMA-IF interfaces the Giga Bus to the SUN Sbus DMA controller SCD 60. The 32Bit Giga Bus enters on P2 the DMA-IF. In an Altera PLD all logic for header recognition is done and the 32Bits of Giga Bus are de-multiplexed to the 16Bit size of the SUN Sbus DMA controller. From Altera, the data are feed into a FIFO. The FIFO output runs into a voltage level conversion circuit with the appropriate signals for SCD20 (TTL) or SCD60 (LVTTL). The appropriate driver circuits are installed at module assembly. The module than can only be used for either SCD20 or SCD60!.

Data-Interface (CS-P-1939 - revision B)

Interface of Gigalink Bus to ULTRA-SPARC DMA controller

Features

• Double Euro size module
• Interface to DMA controller SCD 60
• Data rate 60 MByte/s

General Description

DMA-IF interfaces the Giga Bus to the SUN Sbus DMA controller SCD 60. The 32Bit Giga Bus enters on P2 the DMA-IF. In an Altera PLD all logic for header recognition is done and the 32Bits of Giga Bus are de-multiplexed to the 16Bit size of the SUN Sbus DMA controller. From Altera, the data are feed into a FIFO. The FIFO output runs into a voltage level conversion circuit with the appropriate signals for SCD20 (TTL) or SCD60 (LVTTL). The appropriate driver circuits are installed at module assembly. The module than can only be used for either SCD20 or SCD60!.