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UVES Scientific CCD System
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UVES Blue Hardware Setup and Filter Settings

(see also the   Data for UVES Blue   before   the upgrade on 13/Oct/2004)

Videoboard

  EEV left amp EEV right amp    
Videoboard 0 Channel 0 Channel 1 Channel 2 Channel 3
Gain 0 2 e- / ADU 2 e- / ADU Default Default
Gain 1 0.6 e- / ADU 0.6 e- / ADU Default Default
Resistors ( gain 0 ) R 43 = 300 R // 270 R = 142 R R 47 = 300 R // 270 R = 142 R Default Default
Resistors ( gain 1 ) R 42 = 36 R R 46 = 36 R Default Default
Filter 0 C 21 = 100 pF ( t = 150 ns ) C 25 = 100 pF ( t = 150 ns ) Default Default
Filter 1 C 22 = 220 pF ( t = 500 ns ) C 26 = 220 pF ( t = 500 ns ) Default Default
Filter 2 C 23 = 1 nF ( t = 1.500 ns ) C 27 = 1 nF ( t = 1.500 ns ) Default Default
Filter 3 C 24 = C 374 = 2 nF ( t = 3.000 ns ) C 28 = C 375 = 2 nF ( t = 3.000 ns ) Default Default
Offset setting 0 to 5 V 0 to 5 V 0 to 5 V 0 to 5 V

Note :   Wait statement in wipe line 60000000 ticks to keep IF2 quit ( look up ). Wipe not optimal.



Clockdriverboard

Simm DAC Phase Output Resistor
0 BRD_CLKDRV0 CLKDRV_DAC0 SWL 50 R
1 BRD_CLKDRV0 CLKDRV_DAC1 SWR 50 R
2 BRD_CLKDRV0 CLKDRV_DAC2 RF3 50 R
3 BRD_CLKDRV0 CLKDRV_DAC3 RF2L 50 R
4 BRD_CLKDRV0 CLKDRV_DAC4 RF1L 50 R
5 BRD_CLKDRV0 CLKDRV_DAC5 RF2R 50 R
6 BRD_CLKDRV0 CLKDRV_DAC6 RF1R 50 R
7 BRD_CLKDRV0 CLKDRV_DAC7 DG 50 R
8 BRD_CLKDRV0 CLKDRV_DAC8 IF1 10 R
9 BRD_CLKDRV0 CLKDRV_DAC9 IF2 10 R
10 BRD_CLKDRV0 CLKDRV_DAC10 IF3 10 R
11 BRD_CLKDRV0 CLKDRV_DAC11 empty 10 R
12 BRD_CLKDRV0 CLKDRV_DAC12 FRL 10 R
13 BRD_CLKDRV0 CLKDRV_DAC13 FRR 10 R



Communication Board

Default, no modifications.


Biasboard

Default, no modifications.


Power Supplies

Default,
+ 15 V, 4 A;
- 15 V, 4 A;
+ 30 V, 1 A;
+ 24 V, 5 A;
+ 5 V, 8 A.


DSP Board ( 40 Mhz )

Default, no modifications.


Benner Board

Default, no modifications.


Sparc Computer

Default, no modifications.

UVES Blue Voltage Setup - Global Voltage Definition Table Micro Sequences

This table defines the voltages which will be applied to peripherals at initialisation time. It also defines the high and low limits which may be set for these voltages.


Biasboard 0 for the EEV-CCD 44

Anabias voltages are in 0.001 Volts.

BRD_ID     PERIPH_ID LOW HIGH INIT_VAL USED FOR
Connector P0 - A :
BRD_ANABIAS0 ANB_PRESET_VOLT_A - 3500 - 1000 - 3500 OG1R
BRD_ANABIAS0 ANB_PRESET_VOLT_B - 2500 - 1000 - 2500 OG2R
BRD_ANABIAS0 ANB_PRESET_VOLT_C 20000 26000 23600 ODR
BRD_ANABIAS0 ANB_PRESET_VOLT_D 11000 15000 12500 RDR
BRD_ANABIAS0 ANB_PRESET_VOLT_E 20000 26000 25000 JDR
BRD_ANABIAS0 ANB_PRESET_VOLT_F 20000 26000 25000 JDL
BRD_ANABIAS0 ANB_PRESET_VOLT_G 10000 23000 18500 DDLR
BRD_ANABIAS0 ANB_PRESET_VOLT_H 9000 15000 12500 RDL
Connector P0 - B :
BRD_ANABIAS0 ANB_PRESET_VOLT_I 20000 25000 23600 ODL
BRD_ANABIAS0 ANB_PRESET_VOLT_J - 2500 - 1000 - 2500 OG2L
BRD_ANABIAS0 ANB_PRESET_VOLT_K - 3500 - 1000 - 3500 OG1L
BRD_ANABIAS0 ANB_PRESET_VOLT_L 0 0 0 not used
BRD_ANABIAS0 ANB_PRESET_VOLT_M 0 0 0 not used
BRD_ANABIAS0 ANB_PRESET_VOLT_N 0 0 0 not used
BRD_ANABIAS0 ANB_PRESET_VOLT_O 0 0 0 not used
BRD_ANABIAS0 ANB_PRESET_VOLT_P 0 0 0 not used
The anabias board also has an opto isolated peripheral :
BRD_ANABIAS0 ANB_OPTOOUT 0 32767 255  



Clockdriverboard 0 for the EEV-CCD 44

Clock driver rail voltages are in 0.001 Volts.

BRD_ID     PERIPH_ID LOW HIGH INIT_VAL USED FOR
Connector P0 - A :
BRD_CLKDRV0 CLKDRV_DAC0_LO - 5000 - 5000 - 5000 SWL
BRD_CLKDRV0 CLKDRV_DAC0_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC1_LO - 5000 - 5000 - 5000 SWR
BRD_CLKDRV0 CLKDRV_DAC1_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC2_LO - 5000 - 5000 - 5000 RF3
BRD_CLKDRV0 CLKDRV_DAC2_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC3_LO - 5000 - 5000 - 5000 RF2L
BRD_CLKDRV0 CLKDRV_DAC3_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC4_LO - 5000 - 5000 - 5000 RF1L
BRD_CLKDRV0 CLKDRV_DAC4_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC5_LO - 5000 - 5000 - 5000 RF2R
BRD_CLKDRV0 CLKDRV_DAC5_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC6_LO - 5000 - 5000 - 5000 RF1R
BRD_CLKDRV0 CLKDRV_DAC6_HI 5000 5000 5000
BRD_CLKDRV0 CLKDRV_DAC7_LO - 6000 - 6000 - 6000 DG
BRD_CLKDRV0 CLKDRV_DAC7_HI 6000 6000 6000
Connector P0 - B :
BRD_CLKDRV0 CLKDRV_DAC8_LO - 12000 - 4000 - 8000 IF1
BRD_CLKDRV0 CLKDRV_DAC8_HI - 2000 3000 2000
BRD_CLKDRV0 CLKDRV_DAC9_LO - 12000 - 4000 - 8000 IF2
BRD_CLKDRV0 CLKDRV_DAC9_HI - 2000 3000 2000
BRD_CLKDRV0 CLKDRV_DAC10_LO - 12000 - 4000 - 8000 IF3
BRD_CLKDRV0 CLKDRV_DAC10_HI - 2000 3000 2000
BRD_CLKDRV0 CLKDRV_DAC11_LO 0 0 0 empty
BRD_CLKDRV0 CLKDRV_DAC11_HI
BRD_CLKDRV0 CLKDRV_DAC12_LO - 6000 - 4000 - 6000 FRL
BRD_CLKDRV0 CLKDRV_DAC12_HI 6000 8000 6000
BRD_CLKDRV0 CLKDRV_DAC13_LO - 6000 - 4000 - 6000 FRR
BRD_CLKDRV0 CLKDRV_DAC13_HI 6000 8000 6000

Temperature Sensors   (PULPO.dat)

The upgrade cryostat has some enhancements to that of the existing cryostat. One difference is that the CCD is mounted on a higher thermal conductivity Al-plate rather than an IVAR-plate. Sensor 1 is mounted on this plate and is used to regulate the CCD temperature. For the existing system the temperature is set lower to compensate for the temperature drop between the plate and the CCD. The CCD temperature of the new cryostat can now be set to the correct value. This is done by editing the PULPO.dat file.

Original:

FCDP_PULPO_1 FCDP_HEATER1_SETPOINT 1000 163000 133000 143000
FCDP_PULPO_1 FCDP_HEATER2_SETPOINT 1000 163000 133000 143000
#FCDP_PULPO_1 FCDP_HEATER3_SETPOINT 1000 163000 143000 153000

New for -120°C operation:

FCDP_PULPO_1 FCDP_HEATER1_SETPOINT 1000 163000 143000 153000
FCDP_PULPO_1 FCDP_HEATER2_SETPOINT 1000 163000 143000 153000
#FCDP_PULPO_1 FCDP_HEATER3_SETPOINT 1000 163000 143000 153000

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Last update: Jan 27, 2010
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