AQ four channel

AQ four channel (CS-P-1772- revision A)

Features

• Double Euro size module
• Four 2 MHz ADC’s
• Two different input voltage ranges are scalable
• Four different signal filters - selectable by software
• Delay for ADC convert signal - software controlled up to 3 us by 200 ns steps
• AQ modules can be cascaded
• FIFO buffered ADC data
• Status bus-ID and header number are adjustable by jumpers
• Monitoring of ADC-inputs and the convert signal via front panel LEMO's
• Analog input signals entries the board from the P2 connector on the back pannel
• ADC-Data going out to the giga bus over the DIN-96 connector on the front pannel

General Description

The differential analogue input signals of each channel are input to an instrumentation amplifier followed by a low pass filters in front of the ADCs. A conversion command triggers the ADCs, the data are immediately transferred to a FIFO and then to the output registers. The convert signal has a programmable delay from 0 to 3 usec in steps of 200 nsec.

Each acquisition module can be selected as a master module if the jumper number 8 is not set. It then generates a header code, corresponding to the header, which is set in the status register. Header word followed by the ADC data will put out over the GIGA bus. If the module is not a master, it just puts out the ADC data to the synchronous GIGA bus.

To be synchron to another AQ, there is a signal called "Moving bit". Each module sends his data if the "MovingBitIn" signal is low (low active), after them it generates for the next Aq module the signal "MovingBitOut" and so on...

AQ four channel (CS-P-1772- revision B)

Features

• Double Euro size module
• Four 2 MHz ADC’s
• Two different input voltage ranges are scalable
• Four different signal filters - selectable by software
• Delay for ADC convert signal - software controlled up to 3 us by 200 ns steps
• AQ modules can be cascaded
• FIFO buffered ADC data
• Status bus-ID and header number are adjustable by jumpers
• Monitoring of ADC-inputs and the convert signal via front panel LEMO's
• Analog input signals entries the board from the P2 connector on the back pannel
• ADC-Data going out to the giga bus over the DIN-96 connector on the front pannel
• Absolutely compatible to the version A, but only some bugs was removed

General Description

The differential analogue input signals of each channel are input to an instrumentation amplifier followed by a low pass filters in front of the ADCs. A conversion command triggers the ADCs, the data are immediately transferred to a FIFO and then to the output registers. The convert signal has a programmable delay from 0 to 3 usec in steps of 200 nsec.

Each acquisition module can be selected as a master module if the jumper number 8 is not set. It then generates a header code, corresponding to the header, which is set in the status register. Header word followed by the ADC data will put out over the GIGA bus. If the module is not a master, it just puts out the ADC data to the synchronous GIGA bus.

To be synchron to another AQ, there is a signal called "Moving bit". Each module sends his data if the "MovingBitIn" signal is low (low active), after them it generates for the next Aq module the signal "MovingBitOut" and so on...

AQ four channel (CS-P-1921- revision B)

Features

• Double Euro size module
• Four 2 MHz ADC’s
• Two different input voltage ranges are scalable
• Four different signal filters - selectable by software
• Delay for ADC convert signal - software controlled up to 3 us by 50 ns steps
• AQ modules can be cascaded
• Status bus-ID and header number entries the module over the P2 connector (adjustable on the back plane)
• Monitoring of ADC-inputs and the convert signal via front panel LEMO's
• Only software compatible to the previous versions
• VME compatible
• On board ADC-emulator
• Analog input signals entries the board from the DSUB25 connector on the front pannel

General Description

Each acquisition module will be selected automatically as a master module by the slot-ID (if it is set). It then generates a header code, corresponding to the header, which is set in the status register one. Header word followed by the ADC data will put out over the GIGA bus. If the module is not a master, it just puts out the ADC data to the synchronous GIGA bus.

To be synchron to another AQ, there is a signal called "Moving bit". Each module sends his data if the "MovingBitIn" signal is low (low active), after them it generates for the next Aq module the signal "MovingBitOut" and so on...

The acquisition module has sixteen channels and contains minimum digital logic, so those low-level analog signals are not disturbed by digital noise. The differential analog input signals of each channel are input to a discrete buildup amplifier followed by a low pass filters in front of the ADCs. A conversion command triggers the ADCs. The data are immediately transferred to the output registers. The convert signal has a programmable delay from 750 nsec (offset value) to 3 sec in steps of 50 nsec.. A conversion command triggers the ADCs, which has a convert time of 3 usec and the data are immediately transferred to the output registers. Each two output register (16 bit) send their data at the same time to the GIGA bus (32 bit width) on the P2 connector of backplane. The convert signal has a programmable delay from 0 to 3 sec in steps of 200 nsec.